Subject: TVG info

To: awhitney@haystack.mit.edu

Cc: paul@sgl.crestech.ca (Paul Newby), sasha@sgl.crestech.ca (Sasha Novikov),

        wayne@sgl.crestech.ca (Wayne Cannon)

Hi Alan,

Here is that TVG info. There is a text description and a text table, and

one drawing file is attached as postscript (we have it now in Orcad format

as well). Please note that a second schematic (#2) for the compare circuit

will follow in an upcoming email.

Thanks,

Georg

------------------------ text explanation: vsitvg.txt -----------------------

PROPOSAL FOR A VSI TEST VECTOR GENERATOR

----------------------------------------

REQUIREMENTS

A test vector generator for VSI should have the

following characteristics:

1.  Each TVG output sequence must be different so

    that each connection can be uniquely identified

    and cable wiring errors are detected.

2.  The TVG should be simple to implement and

    easily extendable to provide test signals

    for all data lines as well as a small number

    of lines reserved for non-data signals.

3.  The TVG sequence should repeat at 1 second

    intervals, and should be initialized by the

    1 PPS signal.

3.  It should be possible to enable and disable

    the TVG on command. When enabled the TVG data

    should replace normal user signals.

IMPLEMENTATION

The test vector generator shown in the attached schematic (#1)

implements a 16-bit wide maximal-length sequence with

sequence length of 32767 bits. In addition to the 16 regular

output signals, 16 more test signals are obtained by using the

inverted signals. Beyond this additional test signals are

obtained by exclusive-oring the regular output signals with

the data clock divided by 2.

In other words,

        TVG(0-15) = regular sequence (same as used on S2)

        TVG(16) = -TVG(0)

        TVG(17) = -TVG(1)

        ...

        TVG(31) = -TVG(15)

        TVG(32) = TVG(0) x (clock/2)

        TVG(33) = TVG(1) x (clock/2)

        TVG(34) = TVG(2) x (clock/2)

        etc.

Sequences TVG(32) and higher are not produced with the same

pure statistical quality as maximal length sequences, but

should be adequate for purposes of cable testing. Note that

the schematic does not show enable/disable control and signal

switching logic.

The test vector receiver uses identical generator logic except

that it also includes a compare circuit (see attached schematic #2).

The result of the comparison is a single FAIL bit which may either

be cleared under software control using the CLEARF signal, or

optionally it may be cleared automatically by the read strobe when

reading the FAIL bit, depending on your preference.

----------------------------- table tvg.tab ------------------------

         Table    PROPOSED VSI TVG CABLE TEST VECTOR SEQUENCE

                 (FIRST 20 WORDS FOLLOWING 1Hz RESET AT t=0)

      T T T T  T T T T  T T T T  T T T T  T T T T  T T T T  T T T T  T T T T  T

 Clk  V V V V  V V V V  V V V V  V V V V  V V V V  V V V V  V V V V  V V V V  V

 Per. G G G G  G G G G  G G G G  G G G G  G G G G  G G G G  G G G G  G G G G  G

      [ [ [ [  [ [ [ [  [ [ [ [  [ [ [ [  [ [ [ [  [ [ [ [  [ [ [ [  [ [ [ [  [

      0 1 2 3  4 5 6 7  8 9 1 1  1 1 1 1  1 1 1 1  2 2 2 2  2 2 2 2  2 2 3 3  3

      ] ] ] ]  ] ] ] ]  ] ] 0 1  2 3 4 5  6 7 8 9  0 1 2 3  4 5 6 7  8 9 0 1  2

                            ] ]  ] ] ] ]  ] ] ] ]  ] ] ] ]  ] ] ] ]  ] ] ] ]  ]

  1   0 0 0 0  0 0 0 0  0 0 0 0  0 0 1 0  1 1 1 1  1 1 1 1  1 1 1 1  1 1 0 1  0

  2   0 0 0 0  0 0 0 0  0 0 0 0  1 1 0 0  1 1 1 1  1 1 1 1  1 1 1 1  0 0 1 1  1

  3   0 0 0 0  0 0 0 0  0 0 1 0  1 0 0 0  1 1 1 1  1 1 1 1  1 1 0 1  0 1 1 1  0

  4   0 0 0 0  0 0 0 0  1 1 1 1  0 0 0 0  1 1 1 1  1 1 1 1  0 0 0 0  1 1 1 1  1

  5   0 0 0 0  0 0 1 0  0 0 1 0  0 0 0 0  1 1 1 1  1 1 0 1  1 1 0 1  1 1 1 1  0

  6   0 0 0 0  1 1 0 0  1 1 0 0  0 0 0 0  1 1 1 1  0 0 1 1  0 0 1 1  1 1 1 1  1

  7   0 0 1 0  1 0 1 0  1 0 0 0  0 0 0 0  1 1 0 1  0 1 0 1  0 1 1 1  1 1 1 1  0

  8   1 1 1 1  1 1 1 1  0 0 0 0  0 0 1 0  0 0 0 0  0 0 0 0  1 1 1 1  1 1 0 1  0

  9   0 0 0 0  0 0 1 0  0 0 0 0  1 1 0 0  1 1 1 1  1 1 0 1  1 1 1 1  0 0 1 1  0

 10   0 0 0 0  1 1 0 0  0 0 1 0  1 0 0 0  1 1 1 1  0 0 1 1  1 1 0 1  0 1 1 1  1

 11   0 0 1 0  1 0 0 0  1 1 1 1  0 0 0 0  1 1 0 1  0 1 1 1  0 0 0 0  1 1 1 1  0

 12   1 1 1 1  0 0 1 0  0 0 1 0  0 0 1 0  0 0 0 0  1 1 0 1  1 1 0 1  1 1 0 1  0

 13   0 0 1 0  1 1 0 0  1 1 0 0  1 1 0 0  1 1 0 1  0 0 1 1  0 0 1 1  0 0 1 1  0

 14   1 1 1 0  1 0 1 0  1 0 1 0  1 0 1 0  0 0 0 1  0 1 0 1  0 1 0 1  0 1 0 1  0

 15   0 1 1 1  1 1 1 1  1 1 1 1  1 1 0 1  1 0 0 0  0 0 0 0  0 0 0 0  0 0 1 0  0

 16   0 0 0 0  0 0 0 0  0 0 0 0  1 1 1 0  1 1 1 1  1 1 1 1  1 1 1 1  0 0 0 1  1

 17   0 0 0 0  0 0 0 0  0 0 1 0  0 1 0 0  1 1 1 1  1 1 1 1  1 1 0 1  1 0 1 1  0

 18   0 0 0 0  0 0 0 0  1 1 0 1  1 0 0 0  1 1 1 1  1 1 1 1  0 0 1 0  0 1 1 1  1

 19   0 0 0 0  0 0 1 0  1 1 0 1  0 0 0 0  1 1 1 1  1 1 0 1  0 0 1 0  1 1 1 1  0

 20   0 0 0 0  1 1 1 0  1 1 1 0  0 0 0 0  1 1 1 1  0 0 0 1  0 0 0 1  1 1 1 1  1

  Note: Shown are the first 20 words of test data following

        synchronous 1 Hz reset at sampler clock period t = 0.