Comments by the Space Geodynamics Laboratory (SGL)

                              on the

      Draft Proposal for a VLBI Standard Interface (VSI) Specification 

          Cannon, W.H., Feil, G., Feir, B., Newby, P., Novikov, S.


                             March 5 1999

1.  Electrical interface:
    --------------------

    The proposed electrical interface refers to individual lines
    of balanced ecl, requiring as many as 64 separate lines
    each at 128 Mb/s to achieve 8192 Mbit/sec.  An approach which
    promises to be more efficient and easier to implement is to
    serialize the data into smaller numbers of lines for the purposes
    of transmission from the Data Acquisition System (DAS) to the
    Data Input Box (DIB) and from the Data Output Box (DOB) to the
    Correlator.  For example, Low-Voltage Differential
    Signaling (LVDS) devices are now available for data
    transmission at rates of 1.84 Gbit/sec (460 Mbit/sec on four
    lines), with devices under development for rates of 
    5.37 Gbit/sec (671 Mbit/sec on eight lines).  Another possibility
    is HP's HDMP-1022/HDMP-1024 1.25 GB/s transmitter/receiver.

    In view of the need for long-term continuity of the
    VSI specification, selection of one of these options or 
    a similar alternate should be based on careful consideration
    of both technical suitability and market strength.  

    If a serialized non-ecl method of transmission is used,
    compatibility with hardware having balanced ecl interfaces 
    would require external conversion hardware.


2.  Data Validity:
    -------------

    The proposal calls for data validity to be transmitted
    from the Data Output Box (DOB) to the Correlator, indicating
    "whether the data are believed to be valid or invalid
    on a bit-bit-bit basis."

    Currently it appears that various Correlators deal
    with data validity differently.  Some carry the 
    validity bit through the signal path at full resolution,
    while others ignore it completely.

    In view of the additional hardware complexity involved
    in transporting data validity from the Data Output
    Box (DOB) through the Correlator, alternative methods 
    of communicating data validity (for example, at
    at low bandwidth via a network connection) might be
    considered.

    If a full-bandwidth hardware implementation is indicated,
    it would be desirable to have data and data validity 
    carried on separate cables in order to facilitate 
    direct connection of the Data Acquisition System (DAS) and
    Correlator.  This would also simplify connections to 
    Correlators which have no data validity input.


3.  Data Output Box (DOB) Synchronization:
    -------------------------------------

    Possible methods for synchronizing DOBs are:

    1.  Hardware high-speed clock (e.g. 32 MHz) and hardware 1-Hz tick.
  
    2.  Hardware 1-Hz tick only. Software syncs up internal high-speed clock
       	  using VCO. Offsets to the 1-Hz tick can be specified over the 
       	  communications interface to avoid having to generate different 
       	  moving 1-Hz ticks in hardware.
 
    3.  No hardware signals at all, Correlator sends synchronization command
       	  over communications interface once per second, software syncs up
       	  internal high-speed clock using VCO.

    Methods 2) and 3) would also presumably require a specification
    for the size of the memory buffer on the Correlator in order to
    set a limit on the maximum steady-state timing mismatch between
    the Correlator and DOB.

    Our preference would be to implement timing control using method
    3), but others may require hardware support for methods 1) or 2).